Although the fixed-point number operation has the advantages of fast computation and easy implementation, floating-point (FP) arithmetic offers a larger dynamic range and higher numeric stability. Although fixed-point arithmetic has been used traditionally in FPGA, in this model, the utilization of floating-point arithmetic is preferred for many applications such as advanced signal processing , industrial , wireless communication , and other advanced applications . In those heterogeneous architectures, generally, the FPGA is used as an accelerator to implement the most demanding task of the system. These systems range from large servers for cloud computing to low-power embedded systems for IoT or signal processing. In recent years we are witnessing an enormous acceleration in the inclusion of FPGAs in the basic architecture of computational systems. Furthermore, thanks to the proposed efficient converters between the standard IEEE-754 format and our internal high-radix format, the cost of the input/output conversions in FPGA accelerators is negligible. For applications with similar numbers of additions and multiplications, the high-radix version may be up to 26% faster and even having a wider dynamic range and using higher number of significant bits. We also provide the designer with guidelines on selecting a suitable radix as a function of the ratio between the number of additions and multiplications of the targeted algorithm. Although the high-radix format produces also a significant penalty in the implementation of multipliers, the experimental results show that the adder improvement overweights the multiplication penalty for most of the practical and common cases (digital filters, matrix multiplications, etc.). Since variable shifter implementation (required in any FP adder) has a very high cost in FPGA, high-radix formats considerably reduce the number of possible shifts, decreasing the execution time and area highly. Since vhdl files can be generated in the sub-libraries, despite the generation target being verilog, the script may need to also handle vhdl files, in addition to hex files.This article proposes a family of high-radix floating-point representation to efficiently deal with floating-point addition in FPGA devices with no native floating-point support. Generate_ase_environment.py adds the generated verilog/system verilog files to a list that is appended to the vlog_files.list. Missing hex files during Modelsim simulationĪfter running a simulation on the same design with a hard-coded input value of 2 (0x40000000), the corresponding output is shown incorrectly as 0x00000000.Īs a workaround, I can get the correct output by copying the hex files to ASE's work directory. | |- a10_flt_inv_sqrt_300MHz_altera_fp_functions_171_hcdip5i_memor圜2_uid64_invSqrtTables_lutmem.hexĪs a workaround, I can successfully run make sim by adding the vhdl files in the correct compile order to the generated vhdl_files.list (if there were prior vhdl files in the project).Ģ. | |- a10_flt_inv_sqrt_300MHz_altera_fp_functions_171_hcdip5i_memor圜1_uid61_invSqrtTables_lutmem.hex | |- a10_flt_inv_sqrt_300MHz_altera_fp_functions_171_hcdip5i_memor圜0_uid58_invSqrtTables_lutmem.hex